威盛PD控制器方案 VL105H-Q6 QFN-60封装
Key Features
< CC Logic & PD 3.0 Engine supporting one charging UFP and two DRP DFPs
- Compliant to USB Type-C Cable and Connector Specification Revision 1.3
- Compliant to USB Power Delivery Specification Revision 3.0 Version 1.1
- Integrated Type-C transceivers, supporting one charging UFP and up to two DRP DFPs
- Built-in pull-up/pull down resistors, including Rp, Rd
- Built-in Vconn power switch
- Compliant to VESA DisplayPort Alt Mode on USB Type-C Standard Version 1.0a
- DP mode Discovery/Enter/Exit; DP configure, status update, source/sink connection detection
- Built-in AUX/SBU switch for DP Alt-mode or USB-C analog audio
- Charging connected PD hosts once external power is available
- Supports Provider and Consumer roles
- Supports PD Power Rule up to 100W
- Supports dead battery charging and PD 3.0 Fast Role Swap
- Supports Provider and Consumer roles
- Supports PD Power Rule up to 100W as Sink and 15W as Source
- Either DFP port can charge host (as sink) by first-plugin-first-serve basis, the other port is then set to source mode only
- Built-in D+/D- Charging ePHY for chargers using D+/D- as protocol handshake
- USB Billboard compliant to USB Device Class Definition for Billboard Devices Revision 1.21
- Integrated in-house USB 2.0 Full-speed PHY
- Proprietary design for interchangeable charge through audio to select USB routing by first-plugin-first-serve basis
- Standard 1T 8051 instruction set with embedded Mask ROM and SRAM
- Supports external SPI flash or sharing SPI flash with VLI Hub controller for firmware upgrade
- Built-in trimmed RC oscillator
- 5.0V-to-3.3V LDO and 3.3V-to-1.8V LDO
- Vbus Voltage Detector and Vbus Current Detector for monitoring power safety
- Automatically entering deep power saving mode when connected interface is in idle state
- 15 GPIOs on QFN60 and 11 GPIOs on QFN48 for application customization and one I2C master interface
< Supports QC-to-PD Charge Through