管脚 | 管脚名称 | 电 平 | 说 明 |
1 | VeeT | | Transmitter Ground |
2 | TX_Fault | PECL | Transmitter Fault (LVTTL-O) - High indicates a fault condition |
3 | TX_Disable | PECL | Transmitter Disable (LVTTL-I) – High or open disables the transmitter |
4 | SDA | PECL | Two wire serial interface Data Line (LVCMOS-I/O) (MOD-DEF2) |
5 | SCL | | Two wire serial interface Clock Line (LVCMOS-I/O) (MOD-DEF1) |
6 | MOD_ABS | | Module Absent (Output), connected to VeeT or VeeR in the module |
7 | RS0 | PECL | Rate Select 0 – Not used, Presents high input impedance |
8 | RX_LOS | PECL | Receiver Loss of Signal (LVTTL-O) |
9 | RS1 | | Rate Select 1 – Not used, Presents high input impedance |
10 | VeeR | | Receiver Ground |
11 | VeeR | | Receiver Ground |
12 | RD- | | Inverse Received Data out (CML-O) |
13 | RD+ | | Received Data out (CML-O) |
14 | VeeR | | Receiver Ground |
15 | VccR | | Receiver Power - +3.3V |
16 | VccT | | Transmitter Power - +3.3 V |
17 | VeeT | | Transmitter Ground |
18 | TD+ | | Transmitter Data In (CML-I) |
19 | TD- | | Inverse Transmitter Data In (CML-I) |
20 | VeeT | | Transmitter Ground |